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NXP Semiconductors
LPC11C12/C14
– Do nothing on match.
7.14 System tick timer
The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).
7.15 Watchdog timer
The purpose of the watchdog is to reset the microcontroller within a selectable time
period.
7.15.1 Features
? Internally resets chip if not periodically reloaded.
? Debug mode.
? Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
?
?
?
?
Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 32-bit timer with internal prescaler.
Selectable time period from (T cy(WDCLK) × 256 × 4) to (T cy(WDCLK) × 2 32 × 4) in
multiples of T cy(WDCLK) × 4.
? The Watchdog Clock (WDCLK) source can be selected from the Internal RC oscillator
(IRC), the Watchdog oscillator, or the main clock. This gives a wide range of potential
timing choices of Watchdog operation under different power reduction conditions. It
also provides the ability to run the WDT from an entirely internal source that is not
dependent on an external crystal and its associated components and wiring for
increased reliability.
7.16 Clocking and power control
7.16.1 Crystal oscillators
The LPC11C12/C14 include three independent oscillators. These are the system
oscillator, the Internal RC oscillator (IRC), and the Watchdog oscillator. Each oscillator can
be used for more than one purpose as required in a particular application.
Following reset, the LPC11C12/C14 will operate from the Internal RC oscillator until
switched by software. This allows systems to operate without any external crystal and the
bootloader code to operate at a known frequency.
See Figure 4 for an overview of the LPC11C12/C14 clock generation.
LPC11C12_C14_0
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 00.05 — 23 April 2010
? NXP B.V. 2010. All rights reserved.
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